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Hierarchical test generation for VHDL behavioral models

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3 Author(s)
Rao, S.R. ; Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA ; Bi-Yu Pan ; Armstrong, J.R.

In this method, the VHDL model to be tested is represented by its process model graph (PMG). Test sets for individual processes of the model are precomputed and stored in the design library. The Hierarchical Behavioral Test Generator (HBTG) algorithm accepts the PMG and the precomputed tests as inputs, from which it hierarchically constructs a test sequence that tests the functionality of the model. Such an automatic test generation process relieves the modeler of the time-consuming task of developing test-benches. The test sequence generated by HBTG is then used for simulation of the model. Experimental results indicate that the tests generated exercise the model thoroughly

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993