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Fast technology mapping for multiplexor-based architecture with area/delay tradeoff

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3 Author(s)
Hermann, M. ; Dept. of Electr. Eng., Tech. Univ. of Munich, Germany ; Schlichtmann, U. ; Antreich, K.J.

The authors present enhancements for a BDD-based approach to mapping Boolean networks multiplexor-based architectures like a FPGA by Actel. The algorithm combines the following: transformation of the Boolean network into a mixed BDD/ITE-description, an area-delay tradeoff and effective tree-pruning using a large library. The algorithm performs several times faster than state-of-the-art approaches while delivering competitive results. Its intended usage is the frequent evaluation of the necessary chip area for a given set of Boolean functions in a logic minimization tool

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993