A novel approach to cost-effective estimate of power dissipation in CMOS ICs

An approach to the estimate of power dissipation in CMOS ICs based on the current limited model of MOS transistors able to accurately evaluate current waveforms for all types of digital circuits is presented. The efficiency of the tool developed is such that ICs with up to 10/sup 4/-10/sup 5/ transistors can be cost-effectively treated without any need of arbitrary partitioning. In addition, the algorithm can be used to study problems related to excessive values of supply currents, such as electromigration or noise, and voltage drops on power buses. Results obtained with significant benchmarks are shown in order to demonstrate the accuracy and the efficiency of the proposed method.<
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