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A new accurate and hierarchical timing analysis approach

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3 Author(s)
Blaquiere, Y. ; Dept. of Math. & Comput. Sci., Univ. du Quebec, Montreal, Que., Canada ; Dagenais, M. ; Savaria, Y.

A new and efficient procedure to evaluate the timing performance of VLSI circuits with circuit level accuracy is proposed. The efficiency is obtained by rapidly identifying the critical portions of the circuit at high hierarchical levels with rough delay models. These portions are then successively studied at more detailed levels for maximal accuracy. This procedure, implemented and applied to several circuits, is shown to significantly reduce the analysis time

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993