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An integrated VLSI FIR filter compiler tool targeted at sampling rates from 0 to more than 100 MHz is described. Main features are high-level synthesis and optimization of FIR filter coefficients with respect to frequency specifications, a priori and a posteriori verification of filter response (including finite word length effects), and layout generation based on a bit-parallel architecture. The tool is fully integrated within the GDT environment (Mentor Graphics)
Published in:
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Date of Conference: 22-25 Feb 1993
- Page(s):
- 466 - 471
- Meeting Date :
- 22 Feb 1993-25 Feb 1993
- Print ISBN:
- 0-8186-3410-3
- INSPEC Accession Number:
- 4885215
- Conference Location :
- Paris
- Digital Object Identifier :
- 10.1109/EDAC.1993.386431
- Product Type:
- Conference Publications
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