Synthesis and optimization of asynchronous controllers based on extended lock graph theory

An approach based on extended lock graph theory for synthesizing and optimizing asynchronous circuits from a signal transition graph (STG) specification with multiple transitions is presented. It enables the efficient synthesis of highly concurrent specifications, coming up with solutions where concurrency is reduced taking into account complex timing constraints and avoiding the introduction of unnecessary internal signals. It is relative to a fast logic generation method at the STG level, which permits characterization of a cost function to steer graph transformations for accurate cost measurements