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A digital phase locked loop for power conversion ASICs

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2 Author(s)
Chester, E.G. ; Dept. of Electr. & Electron. Eng., Univ. of Newcastle upon Tyne, UK ; Kinniment, D.J.

It is shown that a digital phase locked loop can be designed to perform the functions of capturing fundamental of an input reference wave, and producing sine and cosine values of the phase angle to a 16 bit accuracy. Digital differential analyzers are used for continuous calculation of the sine and cosine, since the simplicity of the hardware required reduces the number of cells needed for implementation in a gate array ASIC. In the implementation the variable frequency oscillator occupies 2586 cells the phase comparator 2711 cells, PI control 1196 cells, and compensating filters in the loop a total of 3018 cells. Alternative methods would have required a significantly greater area, or placed an additional software burden on an existing processor. While the device is currently being incorporated into a power converter chip aimed at center frequencies of 40-60 Hz, with a lock band of ±8 Hz a wider frequency range is possible with a sacrifice of some accuracy in the output values. A version for motor current control over a frequency range from 0-2000 Hz is being developed

Published in:

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Date of Conference:

22-25 Feb 1993

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