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A quick way to find the optimized performance of a power constrained logic circuit

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2 Author(s)
K. S. Lowe ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; P. G. Gulak

Single-independent path (SIP) analysis is a quick and accurate method for estimating the optimized delay of a logic circuit as a function of power constraint. The technique is based on the realization that a certain class of networks, called SIP, can be easily and precisely optimized by analytic means and that other networks can be accurately approximated by a SIP network. SIP analysis optimizes gate sizes and handles both flat and hierarchical networks. Example results confirm the utility of the technique for a diverse range of applications including network selection, data path optimization, and BiCMOS versus CMOS comparison

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994