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Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI

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6 Author(s)
Kuo, J.B. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Su, K.W. ; Lou, J.H. ; Ma, S.Y.
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This paper presents a device-level analysis of a BiPMOS pull-down structure for low-voltage dynamic BiCMOS logic gate circuit suitable for VLSI using sub-quarter-micron BiCMOS technology. Thanks to the BiPMOS pull-down structure, despite the slow turn-off of the bipolar device, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994