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A 50 MHz 70 mW 8-tap adaptive equalizer/Viterbi sequence detector in 1.2 μm CMOS

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4 Author(s)
G. T. Uehara ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; C. S. H. Wong ; J. C. Rudell ; P. Gray

A new architecture for digital implementation of the adaptive equalizer in Class IV Partial Response Maximum Likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 μm CMOS technology to implement a 50 MHz adaptive equalizer and Viterbi sequence detector dissipating 70 mW from a 3.3 V supply

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994