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A low noise CMOS frequency synthesizer with dynamic bandwidth control

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6 Author(s)
Bayer, M. ; Semicustom Operation, Motorola Inc., USA ; Chomicz, T. ; James, F. ; McEntarfer, P.
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A low noise 0.8 μm CMOS phase locked loop (PLL) with a maximum output frequency of I20 MHz has been developed for a pixel clock generator for a range of computer monitors. Other applications include computer clock generation and disk drives. The synthesizer requires no external components. A low phase noise has been achieved through supply rejection techniques, by placing the oscillator in a high gain feedback loop to minimize its noise contribution, and by dynamically adjusting the PLL bandwidth to maximize the open loop gain

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994

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