SIPPOS (single poly pure CMOS) EEPROM embedded FPGA by news ring interconnection and highway path

A FPGA architecture of two key features is developed. The one is non-volatility with thousands cycles of reprogramming by SIPPOS (single poly pure CMOS) EEPROM which is by standard CMOS process and does not require any additional processing, the other high efficiency of routing/wiring and high speed/low power consumption by a unique hierarchical structure of NEWS (north, east, west, south) ring interconnection and highway path which minimizes number of transfer gates in a path. They are applied to prototype chip design. By this architecture, low cost, non-volatile, high speed and low power FPGA is realized.<
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