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A 1.2 μm CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

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2 Author(s)
Thamsirianunt, M. ; MITEL Semicond., Kanata, Ont., Canada ; Kwasniewski, T.A.

A single-chip, low-power all CMOS PLL frequency synthesizer for digital mobile radio communication systems is presented. The design of PLL components: VCO, dual-modulus prescaler and phase-frequency detector are discussed. Novel circuit techniques and design methodology allow GHz frequency range operation, and result in good phase noise performance. The measured results of a monolithic 1.2 μm CMOS PLL implementation indicate a frequency range of 800 to 900 MHz with -94 dBc/Hz phase noise at a 1 MHz carrier offset, and a power consumption of 18 mW at 5 volts

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994