By Topic

An advanced CMOS EPROM technology for high speed/high density programmable logic devices and memory applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
G. J. Hu ; Cypress Semicond., San Jose, CA, USA ; R. U. Madurawe ; M. Cleeves ; A. Dejenfelt
more authors

A 0.65 μm double-level poly and metal UV EPROM CMOS technology has been developed for high speed complex Programmable Logic Device (PLD) and memory applications. Six types of transistors are used for the high performance designs. In addition to the design rule scaling, the new process includes poly buffer LOCOS (PBL) isolation, borderless contacts/vias. Half the die size and twice the speed on a high density MAX product has been demonstrated compared to a 0.8 μm technology

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994