An advanced CMOS EPROM technology for high speed/high density programmable logic devices and memory applications

A 0.65 /spl mu/m double-level poly and metal UV EPROM CMOS technology has been developed for high speed complex Programmable Logic Device (PLD) and memory applications. Six types of transistors are used for the high performance designs. In addition to the design rule scaling, the new process includes poly buffer LOCOS (PBL) isolation, borderless contacts/vias. Half the die size and twice the speed on a high density MAX product has been demonstrated compared to a 0.8 /spl mu/m technology.<
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