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A 12 bit 1 MHz ACD with 1 mW power consumption

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6 Author(s)
Satou, K. ; Toshiba Corp., Kawasaki, Japan ; Tsuji, K. ; Sahoda, M. ; Otsuka, H.
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A new successive-approximation analog-to-digital (A/D) converter is described. New interpolated C-R DAC, new R-ladder-steering decoder and constant-current comparator have been applied in the A/D converter. By adopting these techniques, high-resolution (12 bit accuracy) and high-speed conversion (1 MHz) with low power consumption (1 mW) has been realized. This chip has been fabricated by double metal and double polysilicon 0.8 μm CMOS process, and the die size is 2.4×1.7 mm 2

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994