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Embedded memory design for a four issue superscaler RISC microprocessor

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17 Author(s)

Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches (2.4 GB/sec) is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshiba's high-speed 0.8 μm CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm×17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70°C and 3.1 V

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994