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A 4.4-ns CMOS 54×54-b multiplier using pass-transistor multiplexer

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7 Author(s)
Ohkubo, Norio ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Suzuki, M. ; Shinbo, T. ; Yamanaka, T.
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A 54×54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77 mm×3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994

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