By Topic

An efficient self-timed queue architecture for ATM switch LSI's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
H. Kondoh ; Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan ; K. Yamanaka ; M. Ishiwaki ; Y. Matsuda
more authors

A new approach to implement queues for controlling ATM switch LSI is presented. We combined a self-timed FIFO with a search circuit that finds the earliest entry for each output port. Using this architecture, queues provided for each output port can be effectively realized by a single FIFO. The delay priority and multicasting are supported without doubling the number of the queues. This new FIFO can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-μm CMOS process technology. Interstage transfer speed over 500 MHz and cycle time over 125 MHz were obtained

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994