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An accurate LNS arithmetic unit using interleaved memory function interpolator

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1 Author(s)
Lewis, D.M. ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada

A logarithmic number system (LNS) arithmetic unit using a new method for polynomial interpolation in hardware is described. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy always uses fewer words of memory than an optimized polynomial with stored polynomial coefficients. Many accuracy requirements for the LNS arithmetic unit are possible, but a round to nearest cannot be easily achieved. The goal suggested here is to ensure that the worst case LNS relative error is smaller than the worst case FP relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second-order polynomial interpolator including approximately 91K bits of ROM

Published in:

Computer Arithmetic, 1993. Proceedings., 11th Symposium on

Date of Conference:

29 Jun-2 Jul 1993