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An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors

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4 Author(s)
J. Dunning ; Motorola Inc., Austin, TX, USA ; G. Garcia ; J. Lundberg ; E. Nuckolls

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 4 )