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Low power analog chips for the computation of the maximal principal component

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3 Author(s)
F. M. A. Salam ; Artificial Neural Networks Lab., Michigan State Univ., East Lansing, MI, USA ; S. S. Vedula ; G. Erten

Test results of two prototype circuit implementations that compute the maximal principal component are described. The implementations are designed to be compact and operate in the subthreshold regime for low power consumption. The prototypes use direct realization of a nonlinear self-learning circuit models which we have developed

Published in:

Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on  (Volume:7 )

Date of Conference:

27 Jun-2 Jul 1994