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Design and evaluation of fault-tolerant interleaved memory systems

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3 Author(s)
Shyue-Kung Lu ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Sy-Yen Kuo ; Cheng-Wen Wu

A highly reliable interleaved memory system for uniprocessor and multiprocessor computer architectures is presented. The memory system is divided into groups. Each group consists of several banks and furthermore, each bank has several memory units. Spare memory units as well as spare banks are incorporated in the system to enhance reliability. Reliability figures are derived to evaluate systems with various amounts of redundancy. The result shows that the system reliability can be significantly improved with little hardware overhead. User transparency in memory access is retained

Published in:

Test Symposium, 1994., Proceedings of the Third Asian

Date of Conference:

15-17 Nov 1994