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Systolic-type implementation of matrix computations based on the Faddeev algorithm

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3 Author(s)
Wyrzykowski, R. ; Dept. of Math. & Comput. Sci., Tech. Univ. of Czestochowa, Poland ; Kanevski, J.S. ; Maslennikov, O.V.

Deals with the problem of enhancing the versatility of VLSI processor arrays without undue addition of hardware, time/control overhead, and software complexity. A promising approach to this problem is based on matrix computations carried out through the Faddeev algorithm. We design a fixed-size, linear array architecture with fully local communications and straightforward control requirements. This high-throughput, systolic-type architecture allows us to minimize both I/O requirements and the number of processing elements performing complicated operations like divisions. To derive the array from a formal description of the Faddeev algorithm based on Gaussian elimination with partial pivoting, we use purposive transformations of the basic dependence graph of the algorithm before its space-time mappings onto array architectures

Published in:

Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on

Date of Conference:

2-6 May 1994

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