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Universal emulations with sublogarithmic slowdown

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3 Author(s)
Kaklamanis, C. ; DIMACS Center, Rutgers Univ., Piscataway, NJ, USA ; Krizanc, D. ; Rao, Satish

The existence of bounded degree networks which can emulate the computation of any bounded degree network of the same size with logarithmic slowdown is well-known. The butterfly is an example of such a universal network. Leiserson was the first to introduce the concept of an area-universal network: a network with VLSI layout area A which can emulate any network of the same size and layout area with logarithmic slowdown. His results imply the existence of an N-node network with layout area O(N log2 N) which can emulate any N-node planar network with O(log N) slowdown. The main results of this paper are: There exists an N-node network with layout area O(N log2 N) which can emulate any N-node planar network with O(loglogN) slowdown. The N-node butterfly (and hypercube) can emulate any network with VLSI layout area N2-ε (ε>0) with O(loglogN) slowdown. We also discuss sublogarithmic bounds for the slowdown of emulations of arbitrary bounded degree networks

Published in:

Foundations of Computer Science, 1993. Proceedings., 34th Annual Symposium on

Date of Conference:

3-5 Nov 1993