Breaking the /spl Theta/(nlog/sup 2/ n) barrier for sorting with faults

We study the problem of constructing a sorting circuit, network, or PRAM algorithm that is tolerant to faults. For the most part, we focus on fault patterns that are random, e.g., where the result of each comparison is independently faulty with probability upper-bounded by some constant. All previous fault-tolerant sorting circuits, networks, and parallel algorithms require /spl Omega/(log/sup 2/ n) depth (time) and/or /spl Omega/(nlog/sup 2/ n) comparisons to sort n items. In this paper, we construct a passive-fault-tolerant sorting circuit with O(nlog nloglog n) comparators, a reversal-fault-tolerant sorting network with O(n log/sup log(2)/ /sup 3/ n) comparators, and a deterministic O(log n)-step O(n)-processor EREW PRAM fault-tolerant sorting algorithm. The results are based on a new analysis of the AKS circuit, which uses a much weaker notion of expansion that can be preserved in the presence of faults. Previously, the AKS circuit was not believed to be fault-tolerant because the expansion properties that were believed to be crucial for the performance of the circuit are destroyed by random faults. Extensions of our results for worst-case faults are also presented.<
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