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A new signal processing technique for d=1 channel codes

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1 Author(s)
Masuo Umemoto ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan

This paper presents a strategy for reducing nonlinearities at high-recording densities; new additional encoding scheme for DC-free d=1 channel codes, and, a partial response (1+D) system with 2-bit decoding. This encoding scheme, which to DC-free codes, reduces by one bit transition interval of d=1 codes, and ensures a wide margin of timing offset. In order to use erasures for the error correction code, the 2-bit decoding scheme is employed in-parallel to detect errors in the decoding procedure. An improvement in the error rate by using parallel decoding is shown.<>

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Magnetics, IEEE Transactions on  (Volume:31 ,  Issue: 2 )