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Performance model for a prioritized multiple-bus multiprocessor system

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2 Author(s)
L. Kurian ; Comput. Sci. and Eng., Univ. of South Florida, Tampa, FL, USA ; Yu-Cheng Liu

The performance of a shared memory multiprocessor system with a multiple-bus interconnection network is studied in this paper. The effect of bus and memory contention is modeled. An analytical model to evaluate the acceptance probability of each processor in such a system is presented. It is assumed that each processor in the system has a distinct priority assigned to it and that arbitration is based on priority. Whenever a request from a processor is rejected due to bus or memory conflicts, the request is resubmitted until granted. Effective memory bandwidth of the system is calculated based on acceptance probability. The accuracy of the analytical model is verified based on simulation results. Results from the model are compared against other models previously reported in literature. It is observed that the inaccuracy of the model measured in terms of error from simulation results is less than errors in previously reported studies

Published in:

Parallel and Distributed Processing, 1994. Proceedings. Sixth IEEE Symposium on

Date of Conference:

26-29 Oct 1994