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Effect of CMOS driver loading conditions on simultaneous switching noise

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3 Author(s)
A. Vaidyanath ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; B. Thoroddsen ; J. L. Prince

A model for simultaneous switching noise (SSN) for CMOS including the effect of negative feedback and loading conditions is presented. A level 1, SPICE-type device model is used with VTN=|VTP | for the simulations. An analysis of the loading conditions is conducted since no prior knowledge of this is assumed in the design of the package. The sensitivity of SSN to the load capacitance is investigated. Equations defining a critical capacitance governing SSN are included. Output buffers normally drive receivers through bond wires, signal traces, pins, and the board traces. For the short trace, the output is modeled as a lumped inductance and for the long trace, as a transmission line. Such a condition at the output will alter the current that defines the noise. Equations are presented for the critical inductance and the transmission line characteristic impedance. Above these critical values, these parameters will tend to decrease the noise generated. Finally, a practical package structure is modeled which takes into account the effects of the total loading conditions

Published in:

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B  (Volume:17 ,  Issue: 4 )