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The MP1 network chip

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2 Author(s)
Jesshope, C. ; Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK ; Izu, C.

Reports on the successful fabrication of a network chip for large-scale parallel computers. It provides extremely low-latency message delivery in grids of up to 1024 processors or toruses of up to 256 processors. Larger arrays can be constructed using an address embedding technique and the gateway channels supported by the chip. This adds little additional cost in terms of latency. The chip supports, without processor intervention, a number of message consumption modes including point-to-point and broadcast message delivery to the processor. The chip provides deadlock-free, adaptive routing over all shortest paths. It has been fabricated in 1.2 micron CMOS and operates at 25 MHz. We have constructed a 16-node backplane using this chip to demonstrate its operation in a heterogeneous message-passing MIMD computer

Published in:

Parallel and Distributed Processing, 1993. Proceedings. Euromicro Workshop on

Date of Conference:

27-29 Jan 1993