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Browse Journals & Magazines > Circuits and Systems I: Funda ...> Volume:41 Issue:11 Help

Impact of distributed gate resistance on the performance of MOS devices

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3 Author(s)
Razavi, B. ; AT&T Bell Labs., Holmdel, NJ, USA ; Ran-Hong Yan ; Lee, K.F.

This paper describes the impact of gate resistance on cut-off frequency (fT), maximum frequency of oscillation (fmax ), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of fT is proven to be independent of gate resistance even for distributed structures. An exact relation for fmax is derived and it is shown that, to predict fmax, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal

Published in:
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:41 ,  Issue: 11 )

Date of Publication: Nov 1994

Page(s):
750 - 754
ISSN :
1057-7122
INSPEC Accession Number:
4833164
Digital Object Identifier :
10.1109/81.331530
Product Type:
Journals & Magazines
Date of Current Version :
06 August 2002
Issue Date :
Nov 1994
Sponsored by :
IEEE Circuits and Systems Society

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