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An OBDD-representation of statecharts

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2 Author(s)
J. Helbig ; Dept. of Comput. Sci., Oldenburg Univ., Germany ; P. Kelb

We present an effective method to translate a statechart into an ordered binary decision diagram (OBDD) representation of its transition system. By that it becomes possible to verify a system specified by a statechart by symbolic model checking, one of the most advanced automatic verification techniques. The method exploits the hierarchy in the relevance of information as is implied by the state structure and admits some redundancy to keep the “decoding effort” of each OBDD small. The method is implemented in the ESPRIT project FORMAT, where OBDD based transition systems serve as a common ground to verify specifications in VHDL or (a variant of) statecharts against temporal logic, symbolic timing diagrams, and each other

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994