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Nondeterministic finite-state machines and sequential don't cares

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1 Author(s)
M. Damiani ; Dipartimento di Elettronica e Inf., Padova Univ., Italy

Nondeterministic finite-state machines are being considered for extracting and representing sequential don't care conditions arising in high-level descriptions. This paper shows that they can also be used for capturing in full the sequential don't cares arising from embedding of a machine in a larger synchronous network in a uniform way. A novel algorithm for synthesizing a minimum-state deterministic finite-state machine from a nondeterministic one is developed here. The techniques developed in this paper are useful when incorporated in a synthesis system extracting sequential don't care information from high-level descriptions

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994