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A new model to uniformly represent the function and timing of MOS circuits and its application to VHDL simulation

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2 Author(s)
J. Frosssl ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; T. Kropf

In this paper a new formal model is presented which allows the uniform representation of the discrete functional and timing behavior of arbitrary MOS transistor circuits. Algorithms are presented to automatically extract the model from transistor netlists and to transform it into VHDL simulation descriptions. The accuracy of the VHDL simulation is sufficient for a detailed functional and timing analysis of digital circuits, although the runtime is considerably reduced. The model is well suited for formal verification approaches since it is based on formalized timed transition systems

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994