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Optimal scheduling and software pipelining of repetitive signal flow graphs with delay line optimization

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4 Author(s)
F. Depuydt ; IMEC, Leuven, Belgium ; W. Geurts ; G. Goossens ; H. De Man

Software pipelining can have an enormous impact on the clock cycle count and hence on the performance of a real-time signal processing design. Because it pays off to invest CPU time in the optimal software pipelining of time-critical parts of a design, an integer programming approach is proposed for simultaneous scheduling and software pipelining. The integer programming techniques in the literature do not support cyclic (repetitive) signal flow, graphs, and/or do not allow optimization of the storage cost of delay lines during software pipelining. The new contributions in this paper are the full integration of software pipelining and scheduling, based on a new timing model that supports cyclic signal flow, graphs and optimization of delay line storage costs. Experiments with several real-time signal processing applications have shown the practical applicability of the approach

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994