Gate-delay fault test with conventional scan-design

In this paper a new algorithm for automatic test pattern generation for finding gate-delay faults will be presented. In contrast to the state-of-the-art approaches the necessary test pattern sequences are generated using the logic function of the circuit to be tested. This enables the usage of both conventional scan flipflops and boundary scan cells, instead of enlarged area-consuming scannable flipflops. Additionally, the test application time can be distinctly reduced since only one test pattern of each test pair has to be loaded into the scan register. Experimental results of the ISCAS-89 benchmark circuits illustrate the efficiency of this new approach