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Massively parallel algorithms for trace-driven cache simulations

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3 Author(s)
Nicol, D.M. ; Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA ; Greenberg, A.G. ; Lubachevsky, B.D.

Considers the use of massively parallel architectures to execute a trace-driven simulation of a single cache set. A method is presented for the least-recently-used (LRU) policy, which, regardless of the set size C, runs in time O(log N) using N processors on the EREW (exclusive read, exclusive write) parallel model. A simpler LRU simulation algorithm is given that runs in O(C log N) time using N/log N processors. We present timings of this algorithm's implementation on the MasPar MP-1, a machine with 16384 processors. A broad class of reference-based line replacement policies are considered, which includes LRU as well as the least-frequently-used (LFU) and random replacement policies. A simulation method is presented for any such policy that, on any trace of length N directed to a C line set, runs in O(C log N) time with high probability using N processors on the EREW model. The algorithms are simple, have very little space overhead, and are well suited for SIMD implementation

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Parallel and Distributed Systems, IEEE Transactions on  (Volume:5 ,  Issue: 8 )