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2400-MFLOPS reconfigurable parallel VLSI processor for robot control

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2 Author(s)
Y. Fujioka ; Tohoku Univ., Sendai, Japan ; M. Kameyama

The architecture of a floating-point reconfigurable parallel VLSI processor is proposed to reduce the latency for robot control, because the computation is performed in a feedback loop. In each processor element, switching hardware is used to change the connection between the multipliers and the adders, so that the multiply-adders having the desired number of multipliers can be reconstructed. Since the data transfer is performed by direct connection between the multipliers and adders, the overhead for data transfer is reduced. The chip evaluation based on 0.8-μm CMOS design rule shows that the latency for resolved acceleration control computation of a twelve-degrees-of-freedom redundant manipulator becomes about 32 μs, which is about sixty times faster than that of a parallel processor approach using conventional digital signal processors

Published in:

Robotics and Automation, 1993. Proceedings., 1993 IEEE International Conference on

Date of Conference:

2-6 May 1993