Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

2400-MFLOPS reconfigurable parallel VLSI processor for robot control

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Fujioka, Y. ; Tohoku Univ., Sendai, Japan ; Kameyama, M.

The architecture of a floating-point reconfigurable parallel VLSI processor is proposed to reduce the latency for robot control, because the computation is performed in a feedback loop. In each processor element, switching hardware is used to change the connection between the multipliers and the adders, so that the multiply-adders having the desired number of multipliers can be reconstructed. Since the data transfer is performed by direct connection between the multipliers and adders, the overhead for data transfer is reduced. The chip evaluation based on 0.8-μm CMOS design rule shows that the latency for resolved acceleration control computation of a twelve-degrees-of-freedom redundant manipulator becomes about 32 μs, which is about sixty times faster than that of a parallel processor approach using conventional digital signal processors

Published in:

Robotics and Automation, 1993. Proceedings., 1993 IEEE International Conference on

Date of Conference:

2-6 May 1993