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A design synthesis system for DSP algorithms based on an optimal multiprocessor scheduler

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1 Author(s)
Kim, H.-K. ; Electron. & Telecommun. Res. Inst., Daejeon, South Korea

This paper describes a design synthesis system which can generate a complete circuit specification efficiently for a given DSP algorithm based on an optimal multiprocessor scheduler. The design synthesis system is composed of two parts: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph (FSFG) as input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the design synthesis process with an example of a second order Gray-Markel lattice filter

Published in:

System Theory, 1994., Proceedings of the 26th Southeastern Symposium on

Date of Conference:

20-22 Mar 1994

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