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Response pipelined CAM chips: the first generation and beyond

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2 Author(s)
K. Ghose ; Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA ; V. A. Dharmaraj

Response-pipelined CAM (RPCAM) chips with W-bit wide words are designed to be cascadable to implement an associative array with a effective word size of K*W bits, where K is a positive integer, and allow a constant search rate of one search per cycle, irrespective of K, without the need for complex wiring or external glue logic. RPCAMs are useful as accelerators for search-intensive applications that use large key sizes. We describe the architecture of the first generation of RPCAMs and an assessment of the 2-micron prototype implementation. We also present an overview of the architecture for the second generation of RPCAMs

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994