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Design of an application specific VLSI chip for image rotation

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2 Author(s)
I. Ghosh ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; B. Majumdar

Design of an ASIC chip for on-line rotation of a digital image is reported here. A CORDIC based scheme has been used to compute the displacement of a pixel. In order to achieve high throughput, the complete image frame is divided into windows and a combination of parallel and pipeline architectures has been developed to compute the rotation of individual windows and for computing the final displacement. The chip offers real time rotation of 512×512 pixel image, with a clock frequency greater than 10.6 MHz. The estimated chip area is 211×276 mils2

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994