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Testable realizations of CMOS combinational circuits for voltage and current testing

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2 Author(s)
K. Biswas ; Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA ; S. Rai

This paper studies the potential invalidation of tests for detecting stuck-on faults derived by neglecting circuit delays. A design for testability (DFT) technique for detecting stuck-open and stuck-on faults using voltage testing in NAND/NAND (NOR/NOR) realizations derived from irredundant sum (product) of prime implicants (implicates) is presented. The proposed design has the advantage over previous designs in that, both single stuck-open and stuck-on faults are detected by tests that are valid in the presence of input as well as circuit delays. A new current testing technique for detecting stuck-open faults in the same class of circuits is also proposed. The advantage of this method over voltage testing is, in this technique stuck-open faults can be detected even if the NAND/NAND realization is part of a larger multilevel circuit

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994