Referenced Items are not available for this document.
An application-specific processor for use as the central component for both signal processing and general control tasks of a combined GPS/Loran-C/Omega/MIS navigation receiver is described. It is the first implementation of the transport-triggered Move architecture framework. Vector registers are included to enhance signal processing performance, resulting in a single-cycle multiply-accumulate operation, without compromising scalar performance. The projected clock frequency of this implementation is 125 MHz for a 180000-transistor, 1.6-μm C MOS sea-of-gates chip
Published in:
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Date of Conference: 11-14 Oct 1992
- Page(s):
- 128 - 131
- Meeting Date :
- 11 Oct 1992-14 Oct 1992
- Print ISBN:
- 0-8186-3110-4
- INSPEC Accession Number:
- 4483018
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ICCD.1992.276192
- Product Type:
- Conference Publications
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