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Test pattern generation for sequential circuits on a network of workstations

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3 Author(s)
Agrawal, P. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Agrawal, V.D. ; Villoldo, J.

A sequential circuit test generation program is parallelized to run on a network of Sparc 2 workstations connected through ethernet. The program attempts to compute tests to detect all faults in a given list. The fault list is equally divided among the processors. The entire process consists of a series of parallel computing passes with synchronization occurring between passes. During a pass, each processor independently generates test sequencies for the assigned faults through vector generation and fault simulation. A fixed per-fault CPU time limit is used within a pass. Faults requiring more time are abandoned for later passes. Each processor simulates the entire fault list with its vectors and communicates the list of undetected faults to all other processors. Processors then combine these fault lists to create a list of faults that were not detected by all processors. This list is again equally divided and the next pass begins with a larger per-fault time limit for test generation. The process stops after either the required fault coverage is achieved or the pass with given maximum per-fault time limit is completed. Some benchmark results are given to show the advantage of distributed system for large circuits. Finally, the authors study a speedup model that considers duplicated computation and interprocessor communication

Published in:

High Performance Distributed Computing, 1993., Proceedings the 2nd International Symposium on

Date of Conference:

20-23 Jul 1993