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Productivity improvement in semiconductor fabrication environment using automode 2E+simulation software

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1 Author(s)
V. Joseph ; Silicon Syst. Inc., Santa Cruz, CA, USA

The development and validation of a wafer fabrication simulation model on Mac II Ci based Automode IIe and the use of this model to improve Fab-2 productivity is discussed. The productivity improvement is achieved by reducing cycle times and work-in-process inventory while increasing factory capacity by optimum utilization of available resources. This study is limited to a 4-in Fab-2 wafer fabrication. This plant uses five bipolar and eight CMOS processes to produce over 46 different devices. The average cycle time is 4.5 weeks for bipolar and 6 weeks for CMOS devices with an average inventory of 8500 wafers in the line at 2000 wafer starts per week. The current product mix is approximately 80% bipolar and 20% CMOS. Both CMOS and bipolar lot size currently being run is 22 wafers per lot. For sizing purposes only one bipolar and one CMOS process was considered even though the model can handle all thirteen processes

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1992. ASMC 92 Proceedings. IEEE/SEMI 1992

Date of Conference:

30 Sep-1 Oct 1992