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MOS device technology trend and future direction

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1 Author(s)
Nakato, T. ; Sharp Microelectronics Technol., Camas, WA, USA

Summary form only given. It is pointed out that IC speed improvements slowed down after achieving 1-μm geometry and will be very slight after 0.5 μm. Scaling down the IC circuit in the depth direction is reaching the limit of existing technology. The real estate for isolation of CMOS SRAM structures occupies more than 80% of the total chip area and the possibility of any great improvement is slim. Although GaAs technology has established its role in a specific high-speed application area utilizing its high electron/hole mobility, its unique material characteristics and high cost make it difficult for GaAs to displace Si. Locally-Ge-implanted Si/GeSi hybrid CMOS fabricated on shallow SIMOX is proposed to overcome these limitations. Junction depths shallower than 0.05 μm, 30% reduction of isolation area, and 40% higher speed should be achievable by using this structure

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1992. ASMC 92 Proceedings. IEEE/SEMI 1992

Date of Conference:

30 Sep-1 Oct 1992