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CMOS cell base implementation of the SPARC architecture

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9 Author(s)
S. T. Wang ; Comput. Integrated Circuit Dept., CCL/ITRI, Hsinchu, Taiwan ; S. J. Lai ; J. Chou ; H. Y. Tarn
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Presents an overview of the TA53017 processor which is the first implementation of the 32-bit RISC based scalable processor architecture (SPARC) CPU chip. The TA53017 (Integer Unit) was fabricated with TSMC's 1.2 um double-metal CMOS technology and completed in the CCL/ITRI's hierarchical cell-based design environment. It operates at a clock rate of 25 MHz and delivers an average performance of 10-15 MIPS, with an external cache and a floating-point coprocessor

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991