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ARES-architecture reinforcing superscalar

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3 Author(s)
Yuh-Haur Lin ; Nat. Taiwan Univ., Taipei, Taiwan ; Feipei Lai ; Meng-chou Chang

In the ARES, there are four major features. First of all, the ARES utilizes both static and dynamic scheduling methods. The instruction identifier bits (IDBs) are attached to each instruction, except jump and branch, to indicate which basic block (BB) the instruction originally belongs to. Thus, the compiler can move instructions across the boundaries of BBs to get more instruction level parallelism. Secondly, the separate architectures memory address calculation from memory access for store instruction. This divides the original two memory cycles of Store instruction for write-back cache into two separate cycles. Thirdly, the system divides the instruction of compare-and-branch into two steps: compare and test-then-branch. With this scheme and branch registers, one can combine the current BB with the following BBs (taken/untaken or both) into one BB to increase the schedulable instructions. Finally, the system follows the same way as the IFU of the MARS system to peep and absorb jump, so there is no delayed slot for jump in the ARES. The architecture can have a 1.62 speedup, compared with the MIPS-X, with a simple extra hardware support

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991

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