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A 64 Mbit DRAM trench capacitor cell with field-plate isolation

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6 Author(s)
Teng, C.W. ; Semicond. Process & Design Center, Texas Instrum., Dallas, TX, USA ; Okumoto, Y. ; Liu, Jiann ; Chen Ih-Chin
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A 2 μm2 field-plate isolated trench capacitor cell for 64 Mbit DRAM has been fabricated and demonstrated. Using 5.5 nm nitride/oxide dielectrics on 6 μm deep trench with 0.6 μm opening, the cell capacitance reaches 45-50 fF/cell. The bitline and word-line capacitances, 0.9 fF/cell and 2.0 fF/cell, respectively, are also favorably low for achieving low power consumption, high access speed, and large sensing signal. Both 0.3 μm field-plate isolation and pass-gate transistor have been realized with minimum narrow-width effect. The trench-to-trench leakage is negligible at operating voltage with 0.5 μm inter-trench space. Fully functional 16 Mbit and 4 K mini-array of 64 Mbit DRAM have been successfully fabricated with data retention time longer than 1 sec at 90°C. These data support that this trench capacitor cell is a viable candidate for the 64 Mbit DRAM

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991