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SCOPE-a s_imultaneous c_o_ntact and p_lanarization e_tch process for low-cost high-performance CMOS applications

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6 Author(s)
K. K. Young ; Hewlett Packard Co., Palo Alto, CA, USA ; W. Uesato ; H. K. Hu ; P. E. Riley
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As CMOS device geometries shrink to below half micron sizes, contact and metal design rules have become the limiting factors for increasing circuit packing density. In order to reduce the contact and metal features accordingly, the process integration issues such as reduced thermal budget, minimized contact size, minimized contact enclosure, dielectric surface planarity, and metal step coverage in the contact must be investigated. In this work, a novel approach is employed to etch contacts and planarize the dielectric in one step. The technique is called SCOPE for Simultaneous COntact and Planarization Etch. The SCOPE process eliminate the need for oxide reflow, thereby minimizing the thermal budget after source/drain formation. It also avoids the need for extensive overetch due to the uniform contact depth, thereby allowing the misaligned contact edges on field oxides

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991